Integrated circuit for digitizer table with dedicated digital signal processor for improved noise immunity

ABSTRACT

A digital tablet of the type that multiplexes pen position signals has filtering and digitizing circuits arranged in separate channels for each of the signals that is to be multiplexed. The tablet pen is connected to receive an oscillator signal and the signal is picked up at each of the four corners of the tablet and applied to the corresponding channel. The separate channels permit the filters to be made sharper. The disclosure also includes improved circuits for processing the pen position signals.

FIELD OF THE INVENTION

This invention relates to an input device for a data processor that iscalled a digital tablet, and more specifically it relates to an improvedorganization of the circuits that process a signal from the tablet.

BACKGROUND General Features of a Digital Tablet

Digital tablets are well known, but it will be helpful to review thefeatures and terminology that particularly apply to this invention. Theuser of a digital tablet positions a device called a "pen" on the tabletsurface, and circuits of the tablet provide a pen position signal to anassociated data processor. The tablet provides a series of positionsamples when the user moves the pen across the surface or while the userholds the pen in a fixed position.

The pen signal is an analog signal--the pen coordinates are representedby the amplitude of the pen signal. In the specific tablet that will bedescribed, the pen signals are current analogues that are converted tovoltage analogues. The tablet circuits digitize the analog pen positionsignals and send the digital coordinates to the computer.

It is a general object in this art to provide good resolution at a highsampling rate. Noise in the signal is a principal limitation toresolution and sampling rate, as will be discussed later.

General Structure of One Type of Tablet

Some tablets have a resistive layer and a user holds a pen over thislayer. Commonly, a dielectric layer spaces an electrode in the tip ofthe pen from the resistive layer. The pen current alternates at aselected frequency and the pen electrode is capacitively coupled to theresistive layer.

The tablet is rectangular and connections for the pen current are madeat each corner of the tablet. The pen current is limited by theresistance of the resistive layer, and the pen position is uniquelydefined by the currents in the paths to the four corners. The resistivelayer is commonly made transparent so that the tablet can mounted infront of a display. The transparent layer is commonly indium-tin oxide,and the layer is sometimes called the ITO layer.

Processing the Pen Position Signal

The analog pen signal is first converted to digital form for each cornerand the digitized signals are supplied to the computer in a timemultiplex sequence (because the computer operates on the four valuessequentially).

Even though the signal generated at the pen is on the order of 12 voltspeak to peak, the small value of the coupling capacitance between thepen tip and the sensor panel results in a pen input signal to the analogfront-end receiver that is in the millivolt range at its maximum. Thissignal has to be extracted to the 10 to 13 bit resolution level. Thesituation is aggravated by three items: first, the digitizer sensorpanel is in the immediate vicinity of the LCD display with all thebacklight drivers active (70 kHz, 120 volts peak to peak); second, theswitching power supply produces noise spikes and third, the noise iscreated by other electronic components within the computer. The resultis that a tablet circuit needs an extremely sharp bandpass filter whichextracts the tiny signal out of a sea of interference.

The Prior Art

The tablet description is based on FIG. 6 of Schlosser, U.S. Pat. No.4,853,493, and it will be helpful to consider this reference in moredetail. An oscillator 136 or 240 provides the excitation source. Adriver amplifier 160-163 is connected to each corner of the tablet andpicks up the oscillator current. Multiplex switches 142-145 connect eachdriver in sequence to apply the oscillator signal to its corner of thetablet. The other three corner connections are held at ground. A pen 134picks up the signal and the signal is amplified by an op amp 184. An opamp 184 is a current to voltage converter. A filter circuit 196 takesout components above or below the oscillator frequency. Block 202 is anamplitude demodulator (as in an a.m. radio). Switch 206 samples thissignal 218 and converts it from analog to digital form.

Nakamura U.S. Pat. No. 4,650,926 is also useful in understanding thesetablets.

SUMMARY OF THE INVENTION

One object of this invention is to provide a tablet with improvedfiltering.

It is a general object in this art to provide a circuit that can beimplemented in an integrated circuit device, and it is a specific objectof this invention to avoid inductors and to use small values ofresistance (the lines are shorter) and small values of capacitance (theelectrode area is smaller).

In the tablet of this invention, the pen is connected to the oscillatorand the tablet signal is picked up at each of the four corners. Aseparate channel is provided for each connection point, and many of thecomponent circuits, including a filter, are located ahead of the outputsequencer or multiplexor. Providing a separate channel for each tabletconnection point provides important advantages. In the known prior art,there is only a single filter and the signals from all the four cornersmust time-multiplex through this filter. However, the switching from onecorner to another presents a step function to the filter in the singlepath at the output of the multiplexor. The filter requires time tosettle out from the step function, and a sharp filter that is desirablefor high resolution in a tablet requires more time to settle out than abroad filter. By putting a filter in each channel according to thisinvention, the filter is given more time to settle out and a sharperfilter can be used. Preferably these filters are implemented digitally.

This goal requires added circuits (one for each channel instead of onefor the output of the multiplexor), and it is another object to providean improved tablet in which these component circuits can be matchedclosely to achieve a closely matched operation for each channel.

The improved component circuits and other features of the invention willbe understood from the description of the preferred embodiment.

THE DRAWING

FIG. 1 is a diagram of a conventional tablet and pen and the signalprocessing components of the preferred tablet system of this invention.

FIG. 2 shows the analog input circuits of a channel of FIG. 1.

FIG. 3 shows the channel circuits, inching the circuits of FIG. 2 inblock form, the sigma-delta analog-to digital converter, and othercircuits that process the tablet signal.

FIG. 4 is a circuit diagram of the sigma-delta modulator shown in blockform in FIG. 3.

FIG. 5 shows a block diagram of the preferred structure of asecond-order bandpass filter using only shifters and adders.

THE PREFERRED EMBODIMENT Overview--FIG. 1

FIG. 1 shows a conventional tablet 12 and pen 13. The preferred tablethas a resistive layer and an overlying dielectric layer that form atablet surface 14. An oscillator 15 is connected to the pen by asuitable cable 16. The pen has an electrode 17 that is capacitivelycoupled to the resistive layer of the tablet. The oscillator has afrequency of 100 khz to several hundred khz, as is conventional. Theinvention is useful with a tablet and pen of various types and thesewell known components will not be described in further detail.

Alternatively, the oscillator could be mounted inside the pen. Theoscillator can be in the form of an integrated circuit chip whichproduces the sine-wave signal required by the tablet system. Theadvantage of this is that the pen in cordless.

Connection points 18 to the resistive layer of the tablet are located ateach of the four corners. A pen signal appears at each corner 18 and aconductor 19 for each corner connection carries the pen signal. In thedrawing, the corner connections and their conductors are identifiedindividually by reference characters with a suffix -1 through -4.Components in the signal path for a corner connection will similarly beidentified individually by a reference character with a suffix in therange -1 to -4 or generally by the reference character without thesuffix. From a more general standpoint the tablet can be rectangular orany suitable shape, and the connections are located at points that areappropriate to establish a coordinate system on the tablet surface. Theywill be called "corner connections" without loss of generality.

One signal processing channel for each corner is connected to receivethe pen signal at the associated corner connection 18. A channel 80,82-84 processes the signal to remove noise and to digitize the signalbut to preserve the pen position information. Each channel includes theanalog section 80, the sigma-delta ADC 82, and the digital signalprocessing filters 84. The analog section converts the current analogsignal to voltage analog, amplifies the signal and filters the highfrequency noise. The sigma-delta ADC 82 then converts the analoguesignal to a digital signal for further processing within the digitalsignal processing block 84. For example, a 13 line bus 52, connects theoutput of the sigma-delta ADC output to the DSP block 84. The output ofthe DSP block 84 connects to the output sequencer 22 for example bymeans of a 16 line data bus 21. The circuits of a channel are shown inFIGS. 2, 3, 4 and 5 and will be described in detail later.

It is an important feature of this invention that this signal processingtakes place in separate channels (ahead of the output sequencer ormultiplexor). An output sequencer 22 combines the channel outputs andproduces an output on a line 24 that has digitized position signals ofall lines 21-1 through 21-4 for the channels in sequence. Suitableoutput sequencers or multiplexors are well known and the outputsequencer or multiplexor will not be described in further detail.

The microcontroller 28 performs known operations on the signal on line24 to derive the pen position. The microcontroller 28 or a differentdata processor also uses this information to perform the operations thata user calls for by positioning the pen on the tablet and to control anassociated display.

The Signal Channel--FIG. 2

The components of FIG. 2 form part of a channel and they are shown againin block form in FIG. 3. An op amp 29 and a feedback resistor 31 forms aknown current to voltage converter 30. A sinusoidal input current on aline 19 is applied to the inverting input, and the op amp produces anoutput voltage that is a function of this current. The feedbackresistors 31 are matched for the four channels.

An op amp 32 forms a standard buffer 33. Note that the input can beswitched to the output of the first op amp for normal operation or to acalibration input for calibration. The calibration input establishes thesame nominal input signal for each channel. If the channels are notidentical, their outputs to the microprocessor 28 will differ duringcalibration, and the microprocessor can use this difference in latercalculating the pen position.

An op amp 34 is connected with an input resistor 35 and a feedbackresistor 36 to form a conventional negative feedback amplifier 37. Theoutput voltage is an inverted function of the input voltage (from thebuffer) and the ratio of the resistors. Resistors 35 and 36 arepreferably formed of polysilicon and are adjusted during manufacture forthe desired gain.

An op amp 38 is connected with resistors 39, 40 and capacitors 41, 42 toform an anti-alias filter 43. An anti-alias filter removes highfrequencies in the signal that could otherwise interact with thesampling frequency (in the sigma-delta modulator 46). The preferredfilter is a second order Sallen-Key low-pass filter; see Millman andGrabel, Microelectronics, McGraw-Hill, 1987, pages 739-743.

The Signal Channel Continued--FIG. 3

FIG. 3 shows the components for channel 80, 82 and 84. All four channelsare identical, and channels 80, 82, 84-2, 80, 82 84-3 and 80, 82, 84-4are indicated in FIG. 3 by their output lines 21-2, 21-3 and 21-4. FIG.3 repeats in functional block form the current to voltage convertercircuit 30, block I/V, blocks 33 and 37 shown collectively as a blockGain Stage, and the anti-alias filter 43 that are shown in circuit leveldetail in FIG. 2.

The Sigma-Delta Modulator and the Decimator

A switched-capacitor sigma delta modulator 46 and a decimator 47 DSP DECconvert the analog sine wave at the output of the anti-alias filter 43to a signal on line 52. This signal is a polarity alternating, sine-likesignal but the amplitude has discrete digitized values so that thewaveform is stair-stepped. The digitized values of the amplitude stepsmake the signal on line 52 significantly immune to noise in the samesense that binary signals are immune to noise that is inherent in anyelectronic circuits.

The sigma-delta modulator produces a series of pulses that have binarylevels ("up" and "down") and have an up time that is proportional to theamplitude of the signal at the input. For example, the output is aseries of progressively wider up level pulses as an unswitched sine wavenears its positive peak, and conversely it is a series of progressivelywider down level pulses as the unswitched wave nears its negative peak.These pulses have a frequency f_(s) which is established by theswitching signal on line 49, as will be explained in the description ofFIG. 4.

The DSP DEC 47 receives the binary valued pulses on line 50 and producesan output 52 with a reduced frequency and with the alternating polaritythat has been described. The output 52 then goes to the block 84 whichwill be described later.

The Sigma-Delta Modulator Circuit--FIG. 4

Circuits of this general type are well known. See Rosert and Wodey, IEEEJournal of Solid State Circuits, vol. 23 No. 6. The signal VIN on theleft in FIG. 4 is the output 44 of the anti-alias filter and the signalY2b on the right is the input 50 to the decimator. An op amp 54 isconnected with capacitors C11 and C13 and switches to form anintegrator. An op amp 56 is similarly connected to form an integrator.The circuit is preferably a second order sigma-delta modulator. Otherorders of modulator could be used.

An amplifier 57 produces a binary output: the signal is either high orlow. Amplifier 57 is followed by an inverter 58 so that the polarity ofthe output is the same as the polarity at V2. A D-type latch 59 receivesthe output of inverter 58. An inverter 60 produces the output on line 50from the output of the latch.

Sample Timing and Operation

The sampling switches operate from timing signals denoted φ1, φ1d, φ2,and φ2d. The sampling frequency of these switches is many times higherthan the Nyquist sampling rate, (in relation to the pen signalfrequency), and in a preferred embodiment is 12 mHz.

Switching waveform φ1d and φ2d rise (the switches close) with waveformsφ1 and φ2 respectively but they fall slightly after φ1 and φ2 fall. Thisdelay assures that the switches at the inverting inputs to the op ampsare opened before the other switches are opened. Switching waveforms φ1,φ1d are non-overlapping with waveforms φ2, φ2.

During the first phase (φ1 and φ1d are up and the associated switchesare closed) the analog input is sampled and the charge is stored incapacitor C11. Similarly, V1, the output of op amp 54, is sampled bycapacitor C21. These timing signals are the same for each channel toavoid timing-related errors. On the fall of φ1, the output of thecomparator is latched into the D-type latch.

The latch output Y2 and its complement Y2B are used to select the properfeedback voltage, VREFP or VREFN, as will be understood from the legendsin the drawing. During phase 2 (φ2 and φ2d are up) the two op amps 54,56 integrate the charges in C11 and C21, multiplied by the values fromthe feedback loops.

The digital signal processor decimator (DSP DEC)--FIG. 3 continued

The output of the sigma-delta modulator is clocked into a row of shiftregisters which are part of a digital finite-impulse response (FIR)filter. The preferred filter is a sinc cubic filter and can be describedby the following z-transform equation. ##EQU1## The term N is the filterlength and M is the finite filter order. The output of the filter issampled at a lower rate, for example 500 khz to form the signal on line52.

The Other Signal Processing Circuits--FIGS. 3 and 5

A circuit 64 provides gain for the output 52 of the decimator. A digitalband pass filter 65, block DSP BPF (digital signal processor band passfilter), removes extraneous frequencies and extracts the frequency ofinterest from the output of the gain stage 64. Since the data rate intothe DSP BPF is at a very high speed (for example about 0.5 Mhz), thesignal processing circuit should be designed as efficient as possible.

A preferred band pass filter 65 can be described by the followingequation. ##EQU2##

The above equation can be implemented very efficiently usingpower-of-two coefficient filters. FIG. 5 shows the arithmetic operationsrequired to implement the equation above.

The input and output to this second-order band pass filter are X and Yrespectively. The symbols 91, 92 and 93 represent a summation operationwithin the digital processor BPF. Symbols 94 and 95 represent unit timedelay between successive data inputs. Symbols 96 and 97 represent a leftshift operation to the binary representation of the input X and outputY. The number of left shifts are represented by the values given in Npand Nz. For example, if Np is equal to 2, the binary representation ofinput X would be shifted left by 2 bit position.

The complete band pass filter is made out of a cascade of severalsecond-order band pass filter as shown in FIG. 5. The operations of sucha standard second-order band pass filter would be understood by thoseworking in the field of digital signal processing.

However, it is thought to be helpful to give the following shortdescription of the operation of FIG. 5. Firstly, the input data X isadded with the data at 101 to produce the output data Y. The data 101 isproduced by the following operations.

Input data X also goes to two other paths, one through the shifter 96and another straight to the adder 93. The shifted value of X issubtracted from X and then added to the feedback of Y within the addoperation 93. The output 98 from this add operation 93, is delayed byone sample delay to produce data at 99. In the add operation 92, thedata 99 is added to the output data Y which has been shifted left by Nzbit positions. The output 100 from the add operation 92 is delayed byone sample delay to produce 101.

With all these arithmetic operation, the pen signal of interest will beextracted from the sea of interferences or interfering frequencies. Notethat this preferred implementation is efficient because it does notrequire any multiplications. This is important because a hardwaremultiplier is slow and takes up a lot of expensive silicon integratedcircuit area.

The center frequency of this band pass filter is at 1/4 of the samplingfrequency. Preferably, two or more zeros are placed at d.c. and at Fs/2to attenuate noise away from the band pass.

The filtered output from the band pass filter is then "full-waverectified" within the rectifier 68. A rectifier circuit 68, block RECT,converts the negative half of this wave to positive polarity. Theoperation is analogous to the detector for an amplitude modulated radiosignal.

A low pass filter 70, block DSP LPF, averages the output of therectifier circuit to form a signal that varies in amplitude with the penposition. The rectified signal has a direct current (d.c.) component andeven harmonics. Because it is difficult to implement sharp and narrowlow pass filtering at high frequencies, the filter is preferably a multirate low pass filter (as indicated by the input, multi-rate LPF); acourse and a wide-band filter is followed by a second filter at a muchlower sampling rate. Block 70 also has conventional circuits thatconvert this amplitude signal to digital code that forms the signal online 21-1 which is supplied to the output sequencer 22. For simplicity,we have illustrated only 21-1 channel output. The other 3 channels areidentical to the channel 1 described above, and their outputs areindicated by line 21-2, 21-3 and 21-4.

The output sequencer 22 receives 4 sets of 16-bit data one set from eachchannel) and then sends these data out serially on line 24 to themicrocontroller 28.

Tracing the Signal and Noise

The circuit can be summarized by tracing the signal from the pen to themicrocontroller. At each connection point the signal has the frequencyof the oscillator and it has a current amplitude that is established bythe voltage of the oscillator and the resistance in the path from thepen to the connection point. Since the resistance of the path from thepen position to the connection is a measure of the path length, thecurrent amplitude represents the path length.

The I/V converter changes the oscillatory current to an oscillatoryvoltage that carries the equivalent information about the path length.The anti-alias filter removes high frequencies that would otherwiseinteract with the sampling frequency to produce noise. Up to this pointin the circuit, the analog signal of interest has a frequency of a fewhundred khz.

The output of the sigma-delta modulator is a series of binary valuedpulses (0 or 1) at the sampling frequency which contains the digitizedinformation of the input signal. The succeeding DSP DEC block increasesthe word-length of the digital representation of the input signal and atthe same time reduces the output data rate. This component is thenfollowed by the DSP BPF which further removes all noise components andextracts the input sinewave. The output is a digitized representation ofthe input sinewave alone with very little residue noise. The RECT andDSP LPF rectify the signal and extract the dc component respectively. Asa result, the output of the DSP LPF is a digital code representationwhich is proportional to the amplitude of the input sinewave signalexcluding the noise.

OTHER EMBODIMENTS

Those skilled in the art will recognize that the tablet can beimplemented with various known component circuits and that the preferredcomponent circuits will be useful in many applications for theinvention.

We claim:
 1. A tablet of the type that multiplexes pen signals from aplurality of connection points (18) to the tablet, the connection pointsbeing spaced apart to define a coordinate system for the tablet surface,and circuits forming a channel (80, 82 and 84) for each tablet surfaceconnection point, wherein the improvement comprises,an analog processingsection (80-1) in each channel connected to an associated connectionpoint of the tablet to receive the corresponding pen signal andproducing an analog output, a sigma-delta modulator section (82-1) ineach channel connected to receive the output of the analog processingsection and producing an alternating polarity signal having digitizedvalues, digital filter means (84-1) in each channel connected to receivethe output of the sigma-delta modulator section and producing a filtereddigital output, and an output sequencer (22) for combining the digitalsignals (21-1, 21-2, 21-3, 21-4) from the digital filter means for eachchannel onto a common line (24).
 2. The tablet of claim 1 wherein thesigma-delta modulator section includes a sigma-delta modulator connectedto receive the output of the analog processing section and a decimatorconnected to receive the output of the sigma-delta modulator and formingthe alternating polarity signal.
 3. The tablet of claim 2 wherein themeans for filtering comprises a digital finite-impulse response filter(47).
 4. A tablet (12) for operation with a data processor (28),comprising,a resistive layer associated with a tablet surface (14), apen (13) having an electrode (17) positionable on the tablet surface, anoscillator (15) and means (16) connecting the oscillator to the penelectrode, whereby the output of the oscillator is coupled to theresistive layer of the tablet when the pen is positioned on the tabletsurface, a plurality of connection points (18) to the resistive layer ofthe tablet, the connection points being spaced apart to define acoordinate system for the tablet surface, a circuit (80, 82, 84) foreach tablet surface connection point for forming a digital signal (21)representing the position of the pen with respect to the associatedconnection point, comprising,a current to voltage converter for forminga voltage signal from the current at the associated corner connection,means for producing a binary valued output at a sampling frequency, andmeans for converting the binary valued outputs to a digitized polarityvarying signal at a selected frequency, and an output sequencer (22) forcombining the digital signals (21-1, 21-2, 21-3, 21-4) from each channelonto a common line (24).
 5. The tablet of claim 4 wherein the means forproducing a binary valued outputs at a sampling frequency includes asigma-delta modulator connected to operate at the sampling frequency. 6.The tablet of claim 5 wherein each circuit (80, 82, 84) for forming adigital signal includesan anti-alias filter (43) connected to supply theinput to the sigma-delta modulator.
 7. The tablet of claim 6 wherein thesigma-delta modulator is connected to produce a signal at the samplefrequency that varies in width according to the amplitude of thesinusoid at the output of the anti-alias filter.
 8. The tablet of claim7 wherein the sigma-delta modulator includes a switched-capacitorintegrator for sampling the signal from the anti-alias filter.
 9. Thetablet of claim 8 wherein the sigma-delta modulator is a second ordersigma-delta modulator.
 10. The tablet of claim 9 wherein each circuitfor forming a digital signal includesmeans connected to the output ofthe sigma-delta modulator (46) for producing a polarity varying signalhaving an amplitude varying in discrete steps.
 11. The tablet of claim10 wherein the means connected to the output of the sigma-deltamodulator includesa decimator for producing the signal with a lowerfrequency than the sample frequency.
 12. The tablet of claim 11 whereina channel includesa band pass filter (65) for the polarity varyingsignal which is connected to the output of said decimator.
 13. Thetablet of claim 12 wherein the means for processing the signal at theoutput of said band pass filter includesmeans for rectifying thepolarity varying signal.
 14. The tablet of claim 13 wherein a channelincludesa low pass filter for averaging the rectified signal and therebyproducing a polarity-invariant signal that varies in amplitude with thepen position at each corner.
 15. The tablet of claim 14 wherein achannel includesmeans for forming a binary code according to theamplitude of the polarity-invariant signal for each corner.
 16. A tabletof the type that multiplexes pen signals from a plurality of connectionpoints (18) to the tablet, the connection points being spaced apart todefine a coordinate system for the tablet surface, wherein theimprovement comprises,an analog processing section (80-1) in eachchannel connected to an associated connection point of the tablet toreceive the corresponding pen signal and producing an analog output, asigma-delta modulator in each channel connected to receive the output ofthe analog processing section and producing a binary valued output, anda decimator connected to receive the output of the sigma-delta modulatorand producing an alternating polarity signal having digitized values,digital finite-impulse response filter means (84-1) in each channelconnected to receive the output of the sigma-delta modulator section,and an output sequencer (22) for combining the digital signals (21-1,21-2, 21-3, 21-4) from the digital filter means for each channel onto acommon line (24).